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isplsi 2032/a in-system programmable high density pld 2032_10 1 use isplsi 2032e for new designs features ? enhancements ? isplsi 2032a is fully form and function compatible to the isplsi 2032, with identical timing specifcations and packaging ? isplsi 2032a is built on an advanced 0.35 micron e 2 cmos ? technology ? high density programmable logic ? 1000 pld gates ? 32 i/o pins, two dedicated inputs ? 32 registers ? high speed global interconnect ? wide input gating for fast counters, state machines, address decoders, etc. ? small logic block size for random logic ? high performance e 2 cmos ? technology ? f max = 180 mhz maximum operating frequency ? t pd = 5.0 ns propagation delay ? ttl compatible inputs and outputs ? electrically erasable and reprogrammable ? non-volatile ? 100% tested at time of manufacture ? unused product term shutdown saves power ? in-system programmable ? in-system programmable (isp?) 5v only ? increased manufacturing yields, reduced time-to- market and improved product quality ? reprogram soldered devices for faster prototyping ? offers the ease of use and fast system speed of plds with the density and flexibility of field programmable gate arrays ? complete programmable device can combine glue logic and structured designs ? enhanced pin locking capability ? three dedicated clock input pins ? synchronous and asynchronous clocks ? programmable output slew rate control to minimize switching noise ? flexible pin placement ? optimized global routing pool provides global interconnectivity description the isplsi 2032 and 2032a are high density program- mable logic devices. the devices contain 32 registers, 32 universal i/o pins, two dedicated input pins, three dedicated clock input pins, one dedicated global oe input pin and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 2032 and 2032a feature 5v in- system programmability and in-system diagnostic capabilities. the isplsi 2032 and 2032a offer non- volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. the basic unit of logic on these devices is the generic logic block (glb). the glbs are labeled a0, a1 .. a7 (figure 1). there are a total of eight glbs in the isplsi 2032 and 2032a devices. each glb is made up of four macrocells. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device. functional block diagram global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) a7 a6 a5 a4 input bus output routing pool (orp) a2 glb logic array dq dq dq dq 0139bisp/2000 copyright ? 2002 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. t el. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com january 2002
specifications isplsi 2032/a 2 use isplsi 2032e for new designs functional block diagram figure 1. isplsi 2032/a functional block diagram global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) a7 a6 a5 a4 input bus output routing pool (orp) a2 clk 0 clk 1 clk 2 goe 0 notes: *y1 and reset are multiplexed on the same pin i/o 0 i/o 1 i/o 2 i/o 3 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i/o 24 i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 18 i/o 17 i/o 16 sdi/in 0 sdo/in 1 i/o 4 i/o 5 y0 *y1/ reset sclk/y2 ispen mode 0139b(1)isp/200 0 the devices also have 32 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, output or bi-directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. eight glbs, 32 i/o cells, two dedicated inputs and two orps are connected together to make a megablock (figure 1). the outputs of the eight glbs are connected to a set of 32 universal i/o cells by the orp. each isplsi 2032 and 2032a device contains one megablock. the grp has as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 2032 and 2032a devices are se- lected using the dedicated clock pins. three dedicated clock pins (y0, y1, y2) or an asynchronous clock can be selected on a glb basis. the asynchronous or product term clock can be generated in any glb for its own clock.
specifications isplsi 2032/a 3 use isplsi 2032e for new designs absolute maximum ratings 1 supply voltage v cc ................................... -0.5 to +7.0v input voltage applied ........................ -2.5 to v cc +1.0v off-state output voltage applied ..... -2.5 to v cc +1.0v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating condition t a = 0 c to + 70 c t a = -40 c to + 85 c symbol table 2 - 0005/2032 v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 4.75 4.5 2.0 0 5.25 5.5 v cc +1 0.8 v v v v commercial industrial capacitance (t a =25 c, f=1.0 mhz) c symbol table 2-0006/2032 c parameter i/o capacitance 7 units typical test conditions 1 2 6 dedicated input capacitance pf pf v = 5.0v, v = 2.0v v = 5.0v, v = 2.0v cc cc i/o in c clock capacitance 10 3 pf v = 5.0v, v = 2.0v cc y data retention specifications table 2-0008a-isp parameter data retention minimum maximum units erase/reprogram cycles 20 10000 ? ? years cycles
specifications isplsi 2032/a 4 use isplsi 2032e for new designs input pulse levels table 2-0003/2032 input rise and fall time 10% to 90% input timing reference levels output timing reference levels output load gnd to 3.0v 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. -135, -150, -180 -80, -110 1.5 ns 3 ns figure 2. test load + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a switching test conditions dc electrical characteristics over recommended operating conditions output load conditions (see figure 2) test condition r1 r2 cl a 470 ? 390 ? 35pf b 390 ? 35pf 470 ? 390 ? 35pf active high active low c 470 ? 390 ? 5pf 390 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2 - 0004a v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using two 16-bit counters. 3. typical values are at v = 5v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007/2032 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current ispen input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 3.5v v v 0v v v (max.) 0v v v 0v v v v = 5v, v = 0.5v v = 0.0v, v = 3.0v f = 1 mhz ol oh in il in cc in il in il cc out toggle il ih condition min. typ. max. units 3 ? 2.4 ? ? ? ? ? ? ? ? ? ? ? ? 0.4 ? 10 -10 -150 -150 -200 v v a a a a ma cc a out ? ? 40 40 ma ma ? ? ?60 ma ? -180, -150 others cc cc comm. industrial
specifications isplsi 2032/a 5 use isplsi 2032e for new designs external timing parameters over recommended operating conditions t pd1 units -150 min. test cond. 1. unless noted otherwise, all parameters use the grp, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2-0030b-180/2032 1 4 3 1 tsu2 + tco1 ( ) -135 min. max. max. description # 2 parameter a1 data prop. delay, 4pt bypass, orp bypass ? 5.5 ? 7.5 ns t pd2 a2 data prop. delay ? ? ns f max a3 clk frequency with internal feedback 154 ? 137 ? mhz f max (ext.) ?4 clk frequency with ext. feedback ? ? mhz f max (tog.) ?5 clk frequency, max. toggle ? ? mhz t su1 ?6 glb reg setup time before clk, 4 pt bypass ? ? ns t co1 a7 glb reg. clk to output delay, orp bypass ? ? ns t h1 ?8 glb reg. hold time after clk, 4 pt bypass 0.0 ? ns t su2 ?9 glb reg. setup time before clk 4.5 ? ns t co2 ?1 0 glb reg. clk to output delay ? ? ns t h2 ?1 1 glb reg. hold time after clk 0.0 ? ns t r1 a1 2 ext. reset pin to output delay ? ? ns t rw1 ?1 3 ext. reset pulse duration 4.5 ? ns t ptoeen b1 4 input to output enable ? ? ns t ptoedis c1 5 input to output disable ? ? ns t goeen b1 6 global oe output enable ? ? ns t goedis c1 7 global oe output disable ? ? ns t wh ?1 8 ext. synchronous clk pulse duration, high 3.0 ? ? ns t wl ?1 9 ext. synchronous clk pulse duration, low 3.0 ? ? ns 111 167 3.0 4.5 ? ? 5.0 ? 8.0 ? 11.0 11.0 5.0 5.0 8.0 -180 min. max. ? 5.0 ? 180 ? ? ? ? ? 0.0 4.0 ? 0.0 ? 4.0 ? ? ? ? 2.5 ? 2.5 ? 125 200 3.0 4.0 ? ? 4.5 ? 7.0 ? 10.0 10.0 5.0 5.0 7.5 100 167 4.0 0.0 5.5 0.0 5.0 3.0 3.0 10.0 4.5 5.5 10.0 12.0 12.0 6.0 6.0
specifications isplsi 2032/a 6 use isplsi 2032e for new designs external timing parameters over recommended operating conditions t pd1 units -110 min. test cond. 1. unless noted otherwise, all parameters use the grp, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2-0030b-110/2032 1 4 3 1 tsu2 + tco1 ( ) -80 min. max. max. description # 2 parameter a1 data propagation delay, 4pt bypass, orp bypass ? 10.0 ? 15.0 ns t pd2 a2 data propagation delay ? ? ns f max a3 clock frequency with internal feedback 111 ? 84.0 ? mhz f max (ext.) ? 4 clock frequency with external feedback ? ? mhz f max (tog.) ? 5 clock frequency, max. toggle ? ? mhz t su1 ? 6 glb reg. setup time before clock, 4 pt bypass ? ? ns t co1 a7 glb reg. clock to output delay, orp bypass ? ? ns t h1 ? 8 glb reg. hold time after clock, 4 pt bypass 0.0 ? ns t su2 ? 9 glb reg. setup time before clock 7.5 ? ns t co2 ? 10 glb reg. clock to output delay ? ? ns t h2 ? 11 glb reg. hold time after clock 0.0 ? ns t r1 a1 2 ext. reset pin to output delay ? ? ns t rw1 ? 13 ext. reset pulse duration 6.5 ? ns t ptoeen b1 4 input to output enable ? ? ns t ptoedis c1 5 input to output disable ? ? ns t goeen b1 6 global oe output enable ? ? ns t goedis c1 7 global oe output disable ? ? ns t wh ? 18 external synchronous clock pulse duration, high 4.0 ? ? ns t wl ? 19 external synchronous clock pulse duration, low 4.0 ? ? ns 77.0 125 5.5 5.5 ? ? 6.5 ? 13.5 ? 14.5 14.5 7.0 7.0 13.0 57.0 83.0 7.5 0.0 9.5 0.0 10.0 6.0 6.0 18.5 8.0 9.5 19.5 24.0 24.0 12.0 12.0
specifications isplsi 2032/a 7 use isplsi 2032e for new designs over recommended operating conditions internal timing parameters 1 t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036c-180/2032 inputs units -150 min. -135 min. max. max. description # 2 parameter 20 input buffer delay ? ? 1.1 ns t din 21 dedicated input delay ? ? 2.4 ns t grp 22 grp delay ? ? 1.3 ns glb t 1ptxor 25 1 product term/xor path delay ? ? 5.0 ns t 20ptxor 26 20 product term/xor path delay ? ? 5.1 ns t xoradj 27 xor adjacent path delay ? ? 5.6 ns t gbp 28 glb register bypass delay ? ? 0.0 ns t gsu 29 glb register setup time before clock ? 0.3 ? ns t gh 30 glb register hold time after clock ? 3.0 ? ns t gco 31 glb register clock to output delay ? ? 0.7 ns 3 t gro 32 glb register reset to output delay ? ? 1.1 ns t ptre 33 glb product term reset to register delay ? ? 4.4 ns t ptoe 34 glb product term output enable to i/o cell delay ? ? 6.4 ns t ptck 35 glb product term clock delay 2.9 5.2 ns orp t ob 38 output buffer delay ? ? 1.2 ns t sl 39 output slew limited delay adder ? ? 10.0 ns 0.6 1.3 grp 0.7 t 4ptbpc 23 4 product term bypass path delay (combinatorial) ? ? 3.6 ns t 4ptbpr 24 4 product term bypass path delay (registered) ? ? 3.6 ns 4.3 4.6 5.0 0.0 2.6 3.1 0.7 1.8 0.8 1.2 2.9 6.9 2.5 4.1 t orp 36 orp delay ? ? 1.3 ns t orpbp 37 orp bypass delay ? ? 0.3 ns 0.8 0.3 outputs 1.3 10.0 t oen 40 i/o cell oe to output enabled ? ? 3.2 ns t odis 41 i/o cell oe to output disabled ? ? 3.2 ns 2.8 2.8 t goe 42 global output enable ? ? 2.8 ns 2.2 t gy0 43 clock delay, y0 to global glb clock line (ref. clock) 2.1 2.3 2.3 ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line 2.1 2.3 2.3 ns clocks 2.1 2.1 t gr 45 global reset to glb ? ? 6.4 ns global reset 4.7 -180 min. max. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0.6 1.1 0.7 ? ? 3.6 4.1 4.8 0.2 2.3 3.1 0.5 1.8 0.7 1.0 2.8 5.9 2.5 3.8 ? ? 0.7 0.2 1.2 10.0 ? ? 2.8 2.8 ? 2.2 1.9 1.9 1.9 1.9 ? 4.1
specifications isplsi 2032/a 8 use isplsi 2032e for new designs internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036c-110/2032 inputs units -110 min. -80 min. max. max. description # 2 parameter 20 input buffer delay ? ? 2.2 ns t din 21 dedicated input delay ? ? 4.8 ns t grp 22 grp delay ? ? 2.6 ns glb t 1ptxor 25 1 product term/xor path delay ? ? 8.8 ns t 20ptxor 26 20 product term/xor path delay ? ? 9.2 ns t xoradj 27 xor adjacent path delay ? ? 10.2 ns t gbp 28 glb register bypass delay ? ? 0.0 ns t gsu 29 glb register setup time befor clock ? 0.1 ? ns t gh 30 glb register hold time after clock ? 6.0 ? ns t gco 31 glb register clock to output delay ? ? 0.4 ns 3 t gro 32 glb register reset to output delay ? ? 2.2 ns t ptre 33 glb product term reset to register delay ? ? 8.8 ns t ptoe 34 glb product term output enable to i/o cell delay ? ? 12.8 ns t ptck 35 glb product term clock delay 5.5 9.5 ns orp t ob 38 output buffer delay ? ? 2.4 ns t sl 39 output slew limited delay adder ? ? 10.0 ns 1.7 3.4 grp 1.7 t 4ptbpc 23 4 product term bypass path delay (combinatorial) ? ? 7.2 ns t 4ptbpr 24 4 product term bypass path delay (registered) ? ? 7.2 ns 6.2 6.8 7.5 0.1 4.9 4.8 0.5 4.0 0.6 1.8 5.9 7.1 4.0 7.0 t orp 36 orp delay ? ? 2.1 ns t orpbp 37 orp bypass delay ? ? 0.6 ns 1.5 0.5 outputs 1.2 10.0 t oen 40 i/o cell oe to output enabled ? ? 6.4 ns t odis 41 i/o cell oe to output disabled ? ? 6.4 ns 4.0 4.0 t goe 42 global output enable ? ? 5.6 ns 3.0 t gy0 43 clock delay, y0 to global glb clock line (ref. clock) 3.2 4.6 4.6 ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line 3.2 4.6 4.6 ns clocks 3.2 3.2 t gr 45 global reset to glb ? ? 12.8 ns global reset 9.0
specifications isplsi 2032/a 9 use isplsi 2032e for new designs isplsi 2032/a timing model glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts i/o pin (input) y0,1,2 grp glb reg bypass orp bypass dq rst re oe ck i/o delay i/o cell orp glb grp i/o cell #24 #25, 26, 27 #33, 34, 35 #43, 44 #36 reset ded. in #21 #20 #28 #29, 30, 31, 32 #38, 39 goe 0 #42 #40, 41 0491/2000 #22 comb 4 pt bypass #23 #37 #45 derivations of t su, t h and t co from the product term clock 1 = = = = t su logic + reg su - clock (min) ( t io + t grp + t 20ptxor) + ( t gsu) - ( t io + t grp + t ptck(min)) (#20+ #22+ #26) + (#29) - (#20+ #22+ #35) (0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5) 2.1 ns = = = = t h clock (max) + reg h - logic ( t io + t grp + t ptck(max)) + ( t gh) - ( t io + t grp + t 20ptxor) (#20+ #22+ #35) + (#30) - (#20+ #22+ #26) (0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1) 1.5 ns = = = = t co clock (max) + reg co + output ( t io + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#20+ #22+ #35) + (#31) + (#36 + #38) (0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2) 7.7 ns table 2- 0042-16/2032 note: calculations are based upon timing specifications for the isplsi 2032/a-180l
specifications isplsi 2032/a 10 use isplsi 2032e for new designs power consumption in the isplsi 2032 and 2032a de- vices depends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 4 shows the relationship between power and operating speed. figure 4. typical device power consumption vs fmax 60 80 100 120406 080 100 120 140 160 180 f max (mhz) i cc (ma) notes: configuration of two 16-bit counters typical current at 5v, 25 c isplsi 2032/a (-150, -180) isplsi 2032/a (-80, -110, -135) 90 70 40 50 0127a/2032a i cc can be estimated for the isplsi 2032/a using the following equation: for 2032/a -150, -180: i cc (ma) = 30 + (# of pts * 0.46) + (# of nets * max freq * 0.012) for 2032/a -135, -110, -80: i cc (ma) = 21 + (# of pts * 0.30) + (# of nets * max freq * 0.012) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 5.0v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 110 120 power consumption
specifications isplsi 2032/a 11 use isplsi 2032e for new designs pin description 1. nc pins are not to be connected to any active signals, vcc or gnd. 2. pins have dual function capability. input/output pins ? these are the general purpose i/o pins used by the logic array. name table 2-0002a-08isp/2032 44-pin plcc pin numbers description 15, 19, 25, 29, 37, 41, 3, 7, 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, i/o 0 - i/o 3 i/o 4 - i/o 7 i/o 8 - i/o 11 i/o 12 - i/o 15 i/o 16 - i/o 19 i/o 20 - i/o 23 i/o 24 - i/o 27 i/o 28 - i/o 31 18, 22, 28, 32, 40, 44, 6, 10 global output enable input pin. 2 goe 0 1, 23 gnd v cc 12, 34 17, 39 6, 28 18, 42 6, 30 vcc no connect. 12, 24, 36, 48 nc 1 ground (gnd) input ? this pin performs two functions. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi/in0 also is used as one of the two control pins for the isp state machine. when ispen is high, it functions as a dedicated input pin. dedicated clock input. this clock input is connected to one of the clock inputs of all the glbs on the device. this pin performs two functions: input ? dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the mode, sdi, sdo and sclk controls become active. reset /y1 y0 sdi/in 0 2 ispen mode input ? when in isp mode, controls operation of isp state machine. - dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or i/o cell on the device. output/input ? this pin performs two functions. when ispen is logic low, it functions as an output pin to read serial shift register data. when ispen is high, it functions as a dedicated input pin. sdo/in 1 2 input ? this pin performs two functions. when ispen is logic low, it functions as a clock pin for the serial shift register. when ispen is high, it functions as a dedicated clock input. this clock input is brought into the clock distribution network and can be routed to any glb and/or i/o cell on the device. sclk/y2 2 - active low (0) reset pin which resets all of the glb and i/o registers in the device. 35 11 14 13 36 24 33 44-pin tqfp pin numbers 48-pin tqfp pin numbers 9, 13, 19, 23, 31 35, 41, 1, 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4 40 5 29 7 8 30 18 27 9, 14, 20, 25, 33, 38, 44, 1, 10, 15, 21, 26, 34, 39, 45, 2, 11, 16, 22, 27, 35, 40, 46, 3, 13, 17, 23, 28, 37, 41, 47, 4 43 5 31 7 8 32 19 29
specifications isplsi 2032/a 12 use isplsi 2032e for new designs pin configuration isplsi 2032/a 44-pin plcc pinout diagram isplsi 2032/a 44-pin tqfp pinout diagram i/o 18 i/o 17 i/o 16 mode reset/y1 vcc sclk/y2 1 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 y0 vcc ispen 1 sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 goe 0 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd 1 sdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 7 8 9 10 12 11 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 6 18 5 19 4 20 3 21 2 22 1 23 44 24 43 25 42 26 41 27 40 28 1. pins have dual function capability. isplsi 2032/a top view 0123b/2032/a i/o 18 i/o 17 i/o 16 mode reset/y1 vcc sclk/y2 1 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 y0 vcc ispen 1 sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 goe 0 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd 1 sdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 isplsi 2032/a top view 1 2 3 4 6 5 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 0851/2032/a 1. pins have dual function capability.
specifications isplsi 2032/a 13 use isplsi 2032e for new designs pin configuration isplsi 2032/a 48-pin tqfp pinout diagram i/o 18 i/o 17 i/o 16 mode reset/y1 2 vcc sclk/y2 2 i/o 15 i/o 14 i/o 13 i/o 12 i/o 28 i/o 29 i/o 30 i/o 31 y0 vcc ispen 2 sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 27 i/o 26 i/o 25 i/o 24 goe 0 gnd i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd 2 sdo/in 1 i/o 8 i/o 9 i/o 10 i/o 11 isplsi 2032/a top view 1 2 3 4 6 5 7 8 9 10 11 35 34 33 32 31 30 29 28 27 26 25 47 13 46 14 45 15 44 16 43 17 42 18 41 19 40 20 39 21 38 22 37 23 48-pin tqfp-2032/a 1 nc 12 1 nc 24 nc 1 36 nc 1 48 1. nc pins are not to be connected to any active signal, vcc or gnd. 2. pins have dual function capability.
specifications isplsi 2032/a 14 use isplsi 2032e for new designs isplsi 2032/a ordering information part number description device number isplsi xxxx xxx x xxx grade blank = commercial i = industrial x speed 180 = 180 mhz f max 150 = 154 mhz f max 135 = 137 mhz f max 110 = 111 mhz f max 80 = 84 mhz f max 2032 2032a power l = low package j = plcc t44 = tqfp t48 = tqfp ? device family 0212a/2032 industrial commercial y l i m a ff ) z h m ( x a m t ) s n ( d p r e b m u n g n i r e d r oe g a k c a p i s l p s i 4 85 1 c c l p n i p - 4 4 4 85 1 p f q t n i p - 4 4 4 85 1 p f q t n i p - 8 4 t able 2-0041b/2032a isplsi 2032a-80lj44i isplsi 2032a-80lt44i isplsi 2032a-80lt48i y l i m a ff ) z h m ( x a m t ) s n ( d p r e b m u n g n i r e d r oe g a k c a p i s l p s i 0 8 10 . 5 c c l p n i p - 4 4 0 8 10 . 5 p f q t n i p - 4 4 0 8 10 . 5 p f q t n i p - 8 4 4 5 15 . 5 c c l p n i p - 4 4 4 5 15 . 5 p f q t n i p - 4 4 4 5 15 . 5 p f q t n i p - 8 4 7 3 15 . 7 c c l p n i p - 4 4 7 3 15 . 7 p f q t n i p - 4 4 7 3 15 . 7 p f q t n i p - 8 4 1 1 10 1 c c l p n i p - 4 4 1 1 10 1 p f q t n i p - 4 4 1 1 10 1 p f q t n i p - 8 4 4 85 1 c c l p n i p - 4 4 4 85 1 p f q t n i p - 4 4 4 85 1 p f q t n i p - 8 4 2a 3 0 2 / a 1 4 0 0 - 2 e l b a t isplsi 2032a-180lj44 isplsi 2032a-180lt44 isplsi 2032a-180lt48 isplsi 2032a-150lj44 isplsi 2032a-150lt44 isplsi 2032a-150lt48 isplsi 2032a-135lj44 isplsi 2032a-135lt44 isplsi 2032a-135lt48 isplsi 2032a-110lj44 isplsi 2032a-110lt44 isplsi 2032a-110lt48 isplsi 2032a-80lj44 isplsi 2032a-80lt44 isplsi 2032a-80lt48
specifications isplsi 2032/a 15 use isplsi 2032e for new designs industrial commercial f ) z h m ( x a m t ) s n ( d p pa ckage ordering number f amily isplsi 0 8 10 . 5 0 8 10 . 5 0 8 10 . 5 4 5 15 . 5 4 5 15 . 5 4 5 15 . 5 7 3 15 . 7 7 3 15 . 7 7 3 15 . 7 1 1 10 1 1 1 10 1 1 1 10 1 4 85 1 4 85 1 4 85 1 2 3 0 2 / a 1 4 0 0 - 2 e l b a t isplsi 2032-180lj isplsi 2032-135lj isplsi 2032-110lj isplsi 2032-80lj isplsi 2032-150lj isplsi 2032-180lt44 isplsi 2032-110lt44 isplsi 2032-80lt44 isplsi 2032-110lt48 isplsi 2032-80lt48 isplsi 2032-135lt44 isplsi 2032-135lt48 isplsi 2032-150lt44 isplsi 2032-180lt48 isplsi 2032-150lt48 44-pin plcc 44-pin plcc 44-pin plcc 44-pin plcc 44-pin plcc 44-pin tqfp 44-pin tqfp 44-pin tqfp 48-pin tqfp 48-pin tqfp 44-pin tqfp 48-pin tqfp 44-pin tqfp 48-pin tqfp 48-pin tqfp y l i m a ff ) z h m ( x a m t ) s n ( d p r e b m u n g n i r e d r oe g a k c a p i s l p s i 4 85 1 c c l p n i p - 4 4 4 85 1 p f q t n i p - 4 4 4 85 1 p f q t n i p - 8 4 ta b le 2-0041c/2032 isplsi 2032-80lji isplsi 2032-80lt44i isplsi 2032-80lt48i

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